CC3C Series

Category: CPU & FPGA

Processor core

• e500 core, 1 GHz, with :
- L1 caches : 32KB Inst. and 32KB Data with parity
- 512 KB of L2 integrated cache or private SRAM
• 1 GB of DDR2 with ECC (2GB on request)
• 256 MBytes of mirror Flash
• 512 KBytes of non volatile RAM
up to 16 GBytes of Nand Solid-state Disk (exclusive with the second SATA port on P2).

I/O subsystem

• two Giga Ethernet ports, available either as 2*1000BT interfaces on front RJ45 connectors or on P2 (factory config)
• One USB2 (High/full speed) on the front and two additionnal channels on P2.
• Temperature sensor
• two RS232 UART 
• two SATA ports on P2 (one exclusive with opt. onboard NAND Flash, one exclusive with 2"5 SATA Disk)
• 1 I2C bus on P1
• 1 SPU bus on P2 (+4 chip select)
• 16 GPIOs on P2 (LVTTL)
• 1 optional XMC slot (PCIe x8, exclusive with 2"5 SATA Disk)


• Engineering kit for debug : JTAG/COP and console.
• Rear Transition Module

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