CP3C-P Series

Category: CPU & FPGA

Main features

Processor Unit

►  one MPC8640 Dual-Core running at 1 GHz (up to 1,25) with :
• L1 cache : 32KB Inst. and 32KB Data
• 1MB of L2 integrated cache with parity
► two DDRII banks (default : 1 GBytes each) with ECC
► 2*128MB Mirror-Bit Flash (up to 2*256 MBytes)
► 512 KB of nvSRAM (non-volatile memory)
► one Calendar clock with supercap backup
► one Elapsed Time Counter
► one thermal monitoring sensor
►  1GB of Soldered NAND flash (up to 8GB/SLC or 16GB/MLC)

Communication subsystem

►  8 lanes available as one PCIe x8 or two PCIe x4 or four PCIe x2 links (hardware setting, opt. 4* x2 possible)
► 2*GigaEthernet ports available either as 2*1000BT inter-faces on front RJ45 connectors or as 2*1000KX (or SGMII) interfaces on P1 (factory setting)
► 2*GigaEthernet ports available either as 2*1000BT inter-faces on front RJ45 connectors or as 2*1000KX (or SGMII) interfaces on P2
► 1* RS232 UART available on a front mini USB connec-tor and P1
► 1* RS422 UART available on P2
► 8* GPIOs on P2 (3.3V LVTTL Level, available as inter-rupt source)
► 16* differential pairs (optional thanks to an expansion mezzanine)
► Status Leds
►  PIC µ-controller for System Management (per VITA 46.11)

Accessories
► Engineering kit for debug : JTAG/COP, console,...
► 3U Rear Transition Module

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